IP Logic Design Engineer

Full Timesenior

Rancho Cordova, CA, United StatesPosted 17 days ago

Role Overview

Solidigm is hiring a senior-level IP Logic Design Engineer. This is a full-time role in Rancho Cordova. posted 2 weeks ago. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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Job description

Join Solidigm’s visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology.

Job responsibilities include, but not limited to:

Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off
Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers
Contribute to next-gen 3D NAND architecture and pathfinding to improve density, die-size, performance, power, and cost
Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features
Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks
Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality
Support post-silicon debug and failure analysis across multiple configurations

MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience
Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO
Experience with lint tools, CDC/RDC analysis, and timing constraints
Strong background in design verification tools and automation scripting
Prior experience in 3D NAND Flash Memory logic design is a plus
Ability to work independently across pre- and post-silicon debug cycles

The compensation range for this role is $105,440 - $164,800. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

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Frequently Asked Questions

How do I apply for the IP Logic Design Engineer position at Solidigm?

Use the Apply button above to submit your application directly to Solidigm. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the IP Logic Design Engineer position at Solidigm located?

This position is based in Rancho Cordova. Solidigm has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a IP Logic Design Engineer at Solidigm earn?

Solidigm has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the IP Logic Design Engineer role at Solidigm posted?

This role was posted on June 22, 2026 (17 days ago). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.

How much experience does the IP Logic Design Engineer role at Solidigm require?

This is a senior-level position. Most senior roles call for 5+ years of directly relevant experience. Solidigm lists their specific requirements in the description below, so review the must-have qualifications closely before applying.