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FPGA Engineer

Scalian
Full TimeMid Level
San Diego, CA, United StatesPosted 12 weeks ago

Role Overview

Scalian is hiring a mid-level FPGA Engineer. This is a full-time role in San Diego. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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PythonLinuxORComplianceAsFPGAEngineerASIC

Job description

As an FPGA Engineer, you will play a key role in designing, verifying, and implementing complex digital hardware solutions for aerospace and defense applications, including navigation, timing, and actuation systems. Your primary focus will be on developing reliable, high-performance FPGA/ASIC designs that meet stringent safety, quality, and performance standards.

You will collaborate with system architects, hardware engineers, and verification teams to support the full development lifecycle from requirements definition and RTL design through verification, integration, and validation. This role is central to delivering robust, safety-critical hardware solutions that enable advanced avionics and embedded systems.

  • Design and develop RTL modules using VHDL/Verilog for FPGA and ASIC targets based on system requirements
  • Build and execute verification environments, including testbenches and simulation models, using SystemVerilog/UVM methodologies
  • Develop scripts (Python, Tcl, Perl) to automate simulation, testing, and validation workflows
  • Ensure compliance with DO-254 standards for safety-critical hardware development
  • Utilize tools such as Xilinx Vivado/Vitis for synthesis, implementation, and debugging
  • Work with industry-standard communication protocols such as PCIe, ARINC 429, SPI, and MIL-STD-1553
  • Collaborate with cross-functional teams on system integration and hardware/software co-design
  • Debug RTL issues and validate designs on laboratory hardware test benches
  • Analyze code and functional coverage to ensure design robustness and completeness
  • Document design processes, verification results, and technical specifications to support certification and continuous improvement
  • Bachelor’s or Master’s degree in Electrical or Electronics Engineering or a related field
  • 5–8 years of experience in FPGA/ASIC design and verification (level dependent)
  • Strong proficiency in VHDL and/or Verilog, with experience in UVM/SystemVerilog for verification
  • Hands-on experience with FPGA development tools such as Xilinx Vivado (Vitis is a plus)
  • Familiarity with simulation tools such as QuestaSim, ModelSim, or VCS
  • Solid understanding of digital design principles and hardware development workflows
  • Experience working with communication protocols such as PCIe, ARINC 429, SPI, or MIL-STD-1553
  • Knowledge of DO-254 level C or more critica Exposure to scripting languages (Python, Tcl, Perl) for automation and testing
  • Strong problem-solving skills and ability to debug complex hardware issues
  • Effective communication and collaboration skills for working across multidisciplinary teams
  • Experience in domains such as digital signal processing, image processing, or embedded systems (C/C++, embedded Linux) is a plus

About Scalian

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Scalian

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Frequently Asked Questions

How do I apply for the FPGA Engineer position at Scalian?

Use the Apply button above to submit your application directly to Scalian. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the FPGA Engineer position at Scalian located?

This position is based in San Diego. Scalian has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a FPGA Engineer at Scalian earn?

Scalian has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the FPGA Engineer role at Scalian posted?

This role was posted on April 17, 2026 (84 days ago). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.

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