Senior Design Verification Engineer

Full Timesenior

Toronto, Ontario, CanadaPosted 3 days ago

Role Overview

Asteralabs is hiring a Senior Design Verification Engineer. This is a full-time role in Toronto, Ontario. posted 3 days ago. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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PythonExpressORAsteraLabsNASDAQALABAI

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description 

We are looking for a Senior Design Verification Engineer with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation. 

Basic Qalifications: 

Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is 
required, and a Maser’s is preferred. 
≥2 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or 
Networking applications. 
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for 
customer meetings in advance, and to work with minimal guidance and supervision. 
Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! 
Authorized to work in Canada and start immediately.

Required Experience:

Experience with integrating C/C++ in System Verilog environments using DPI/PLI 
Ability to use scripting tools (Perl/Python) to automate verification infrastructure. 
Experience in developing infrastructure and tests in a hybrid directed and constrained random 
environments 
Must be able to work independently to develop test-plans, and related test-sequences in UVM to 
generate stimuli and work collaboratively with RTL designers to debug failures. 
Develop user-controlled random constraints in transaction-based verification methodology. Experience 
writing assertions, cover properties and analyzing coverage data 
Must have prior experience using Verification IPs from 3rd party vendors for communication protocols 
such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc. 
Develop VIP abstraction layers to simplify and scale verification deployments

Preferred Experience:

S/W debugging for SoC based designs in the area of kernel/device-drivers/u-boot 
Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol. 
Experience in memory technologies like DDR4/DDR5/HBM. 
Experience with FPGA-based verification/emulation.

Base salary range is $125,000 CAD -$180,000 CAD, and will be determined based on the candidate's capabilities and employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Asteralabs

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Frequently Asked Questions

How do I apply for the Senior Design Verification Engineer position at Asteralabs?

Use the Apply button above to submit your application directly to Asteralabs. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the Senior Design Verification Engineer position at Asteralabs located?

This position is based in Toronto, Ontario. Asteralabs has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a Senior Design Verification Engineer at Asteralabs earn?

Asteralabs has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Senior Design Verification Engineer role at Asteralabs posted?

This role was posted on July 8, 2026 (3 days ago). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.

How much experience does the Senior Design Verification Engineer role at Asteralabs require?

This is a senior-level position. Most senior roles call for 5+ years of directly relevant experience. Asteralabs lists their specific requirements in the description below, so review the must-have qualifications closely before applying.