Technical Lead Design Verification Engineer

Full TimeHybrid

San Jose, California, United StatesPosted 16 days ago

Role Overview

Asteralabs is hiring a Technical Lead Design Verification Engineer. This is a full-time hybrid role, based in San Jose, California. posted 2 weeks ago. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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PythonExpressORAsteraLabsNASDAQALABAI

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You’ll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.

Basic qualifications

Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Masters is preferred.
≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications.
Knowledge of industry-standard simulators, revision control systems, and regression systems.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately.

Required Experience

Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
Proven ability to mix and deploy hybrid techniques as in both directed and constrained random.
Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus.
Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out.

Preferred Experience

Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
Experience with directed test based methodologies, cache verification and formal methods.

The base salary range is USD 160,000.00 – USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Asteralabs

Asteralabs

Hybrid

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Frequently Asked Questions

How do I apply for the Technical Lead Design Verification Engineer position at Asteralabs?

Use the Apply button above to submit your application directly to Asteralabs. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Is the Technical Lead Design Verification Engineer role at Asteralabs remote or in-office?

This is a hybrid role based in San Jose, California. Expect a mix of in-office and remote days, with the specific cadence set by the hiring manager.

What does a Technical Lead Design Verification Engineer at Asteralabs earn?

Asteralabs has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Technical Lead Design Verification Engineer role at Asteralabs posted?

This role was posted on June 25, 2026 (16 days ago). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.