Principal Signal and Power Integrity Engineer

San Jose, CA Posted 9 days ago

Role Overview

Asteralabs is hiring a Principal Signal and Power Integrity Engineer. This is a full-time role in San Jose. Part of Asteralabs's Data Science hiring, posted last week. Full responsibilities, required qualifications, and the apply link are listed in the description below.

Salary Context

Salary is not disclosed in this posting. Market median for Principal-level Data Science roles is $188k-$241k (based on 11 comparable listings). Many employers share specifics during the interview process or after an initial screen.

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ORAsteraLabsNASDAQALABAIByIntelligent

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.

Basic Qualifications

Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.
8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
Cross-functional design mentality with the electrical design community to develop systems.
Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
Proven track record solving problems independently, preferably as a tech lead.
Entrepreneurial, open-minded behavior, and can-do attitude.
Authorized to work in the US and start immediately.

Required Experience

Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets
EM modeling of BGA and connector structures
High-speed SERDES channel simulation, and equalization
PI simulations with Ansys/Cadence toolsets
Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
Working knowledge of PCB fabrication limits and trade-offs
Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.
Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Asteralabs

Asteralabs

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Frequently Asked Questions

How do I apply for the Principal Signal and Power Integrity Engineer position at Asteralabs?

Use the Apply button above to submit your application directly to Asteralabs. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the Principal Signal and Power Integrity Engineer position at Asteralabs located?

This position is based in San Jose. Asteralabs has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a Principal Signal and Power Integrity Engineer at Asteralabs earn?

Asteralabs has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Principal Signal and Power Integrity Engineer role at Asteralabs posted?

This role was posted on July 2, 2026 (9 days ago). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.

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