Physical Design/CAD Engineer

Full Timejunior

San Jose, California, United StatesPosted 10 days ago

Role Overview

Asteralabs is hiring a entry-level Physical Design/CAD Engineer. This is a full-time role in San Jose, California. posted last week. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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PythonORIPAsteraLabsNASDAQALABAI

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person.

Key Responsibilities

As Physical Design CAD Engineer you will support and build flows for world class EDA tools.
Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems.
Architect and recommend flow improvements and enhance existing methodology for high performance design.
Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc.
Work with cross function teams to define requirements and specifications to achieve best PPA
Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity
Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.

Basic Qualifications

Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
2-10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
Strong scripting ability (Tcl, Python, Perl).
Ability to work independently with strong prioritization and a professional, customer-focused mindset.

Preferred Experience

Knowledge of agentic AI solutions is a plus.
Experience working with EDA/IP vendors for both RTL and hard-macro integration.
Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
Knowledge of ECO methodologies, DFT tools, and test coverage analysis.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Asteralabs

Asteralabs

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Frequently Asked Questions

How do I apply for the Physical Design/CAD Engineer position at Asteralabs?

Use the Apply button above to submit your application directly to Asteralabs. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the Physical Design/CAD Engineer position at Asteralabs located?

This position is based in San Jose, California. Asteralabs has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a Physical Design/CAD Engineer at Asteralabs earn?

Asteralabs has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Physical Design/CAD Engineer role at Asteralabs posted?

This role was posted on July 1, 2026 (10 days ago). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.

Is the Physical Design/CAD Engineer role at Asteralabs entry-level?

Yes. This is an entry-level position. Strong candidates typically have 0-2 years of relevant work experience, internships, or significant project work. Read the full description for any specific qualification requirements Asteralabs has listed.