Analog IC Design Engineer, Tech Lead

Full Timelead

Mountain View, CA; Toronto, ONPosted Yesterday

Role Overview

Lightmatter is hiring a Analog IC Design Engineer, Tech Lead. This is a full-time role in Mountain View, CA; Toronto. posted yesterday. Full responsibilities, required qualifications, and the apply link are listed in the description below.

Resume Keywords to Include

Make sure these keywords appear in your resume to improve ATS scoring

PythonMATLABORCompensationBenefitsIPLightmatterAI

Job description

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads.

Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter!

If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders.

Lightmatter is (re)inventing the future of computing with light!

About this Role

Join a cutting-edge team at the forefront of silicon photonics and high-speed transceiver design! As a member of the analog team, you’ll collaborate with our architects and engineers to develop innovative high-speed analog transceiver solutions for next-generation optical and wireline communication systems.

Responsibilities

Design high-performance and high-speed AMS circuits with a focus on transceivers and broadband circuits interfacing with silicon photonics elements
Investigate and evaluate new Analog & Mixed-Signal circuit topologies with chip architects
Lead the discussions with multi-functional teams (system, digital, analog, photonics) to create and drive block-level specifications, mixed-signal implementations, and behavioral modeling
Document design simulations and verifications towards formal design reviews
Drive block-level floorplan, mask design views, and their reviews
Run post-layout and mixed-signal top-level simulations to validate integration
Define production and bench-level test plans
Validate performances of the circuits in the lab
Mentor junior design engineers

Qualifications

MS with 12+ years of industry experience, OR Ph.D with 10+ years of industry experience designing in either GHz-speed RF or GHz-speed broadband analog design
Experience designing Analog-Front-End blocks for SerDes
Experience and deep understanding of Tx/Rx equalization techniques and circuits
Excellent understanding of CMOS device characteristics, noise, linearity, high-frequency circuit theory and design trade-offs
Proven experience working with system and architecture teams to drive block-level and IP requirements
Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g., SystemVerilog, Matlab, Python, VerilogAMS)
Experience with 3D Electro-Magnetic (EM) simulation tools
Prior experience in leading or mentoring junior design engineers
Ability to work collaboratively with people across multiple functional areas

Preferred Qualifications

Experience designing Analog-Front-End blocks for transceiver circuits such as trans-impedance amplifiers (TIA) and Tx Driver
Experience interfacing with silicon photonic modulators (MZM, Ring)
Hands-on design experience in advanced CMOS technologies, such as FinFET
Successful track record in delivering analog/mixed-signal IPs with 1st-time success while meeting tight schedules

We offer competitive compensation. The base salary range for this role determined based on location, experience, educational background, and market data.

Salary Range: total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.

$230,000—$270,000 USD

Benefits

Comprehensive Health Care Plan (Medical, Dental & Vision)
Retirement Savings Matching Program
Life Insurance (Basic, Voluntary & AD&D)
Generous Time Off (Vacation, Sick & Public Holidays)
Paid Family Leave
Short Term & Long Term Disability
Training & Development
Commuter Benefits
Flexible, hybrid workplace model
Equity grants (applicable to full-time employees)

Benefits eligibility may vary depending on your employment status and location. Lightmatter recruits, employs, trains, compensates, and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.

Export Control

Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.

About Lightmatter

Lightmatter

On-site

54 other open roles at Lightmatter on TryApplyNow.

View all 55 roles at Lightmatter

Frequently Asked Questions

How do I apply for the Analog IC Design Engineer, Tech Lead position at Lightmatter?

Use the Apply button above to submit your application directly to Lightmatter. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the Analog IC Design Engineer, Tech Lead position at Lightmatter located?

This position is based in Mountain View, CA; Toronto. Lightmatter has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a Analog IC Design Engineer, Tech Lead at Lightmatter earn?

Lightmatter has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Analog IC Design Engineer, Tech Lead role at Lightmatter posted?

This role was posted on July 9, 2026 (yesterday). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.