Senior Distributed Systems Engineer - EDA/VLSI Platform

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SAN JOSEPosted Today

Role Overview

Cadence Design Systems is hiring a Senior Distributed Systems Engineer - EDA/VLSI Platform. This is a full-time role in SAN JOSE. posted today. applications are still in the early window, before most candidates have applied. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the Role

We're building a next-generation distributed transistor-level electromigration and IR drop analysis tool. Our team has strong expertise in numerical solvers and circuit simulation algorithms. We need an experienced distributed systems engineer to design the scalable data processing infrastructure for handling massive circuit designs across distributed computing resources.

What You'll Build

Architect and develop the core distributed infrastructure for a Python-based platform orchestrating high-performance C++ solvers, focusing on:

Data Pipeline & I/O Management

Efficient ingestion pipelines for large-scale netlists and simulation data
High-performance I/O for multi-TB circuit databases
Serialization/deserialization layers bridging Python and C++ components
Streaming results from distributed solver instances

Job Orchestration & Workflow

Task distribution architecture with fault-tolerant scheduling for long-running simulations
Resource management and load balancing across compute clusters
Monitoring and observability for distributed workflows
Optimization of task granularity and dependency management

Visualization & Analytics

Scalable visualization for multi-dimensional TB-scale simulation results
Interactive data exploration and optimization techniques (downsampling, LOD, progressive rendering)

Required Expertise

Distributed Systems

5+ years building production distributed systems with Python
Deep experience with Dask Distributed or similar frameworks (Spark, Ray, Celery)
Strong grasp of distributed computing patterns, data locality, and fault tolerance

Data Engineering

Expertise in high-performance I/O (HDF5, Parquet, Arrow, columnar formats)
Data partitioning strategies, memory-mapped files, zero-copy techniques, streaming patterns
Python/C++ interop (pybind11, Cython, ctypes)

Big Data Visualization

Experience with large-scale scientific/engineering visualization systems

Nice to Have

Background in EDA, VLSI, semiconductor design, or computational engineering
HPC experience with job schedulers (Slurm, PBS, LSF)
GPU acceleration knowledge
Familiarity with modern languages, tools (Go, Plotly, Bokeh, Holoviews, Datashader)
Open-source distributed computing contributions

Why Join Us

We bring strong expertise in numerical methods and circuit analysis algorithms, well-defined solver interfaces, and a clear technical vision. You'll build greenfield distributed infrastructure with modern tools, designing the scalable foundation that makes advanced analysis capabilities accessible to chip design engineers.

Ideal Candidate

You're a systems thinker excited about data pipeline architecture and production-scale distributed systems. You understand orchestrating heterogeneous workloads and designing elegant abstractions for distributed computing. You prioritize observability, fault tolerance, and user experience alongside performance.

No circuit simulation expertise needed—that's our strength. We need your expertise building scalable, reliable infrastructure.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

About Cadence Design Systems

Cadence Design Systems

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Frequently Asked Questions

How do I apply for the Senior Distributed Systems Engineer - EDA/VLSI Platform position at Cadence Design Systems?

Use the Apply button above to submit your application directly to Cadence Design Systems. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the Senior Distributed Systems Engineer - EDA/VLSI Platform position at Cadence Design Systems located?

This position is based in SAN JOSE. Cadence Design Systems has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a Senior Distributed Systems Engineer - EDA/VLSI Platform at Cadence Design Systems earn?

Cadence Design Systems has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Senior Distributed Systems Engineer - EDA/VLSI Platform role at Cadence Design Systems posted?

This role was posted on July 24, 2026 (today). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.

How much experience does the Senior Distributed Systems Engineer - EDA/VLSI Platform role at Cadence Design Systems require?

This is a senior-level position. Most senior roles call for 5+ years of directly relevant experience. Cadence Design Systems lists their specific requirements in the description below, so review the must-have qualifications closely before applying.