Mixed Signal Systems and Verification Engineer II

Full Timemid

MOUNT-ROYAL (Montreal)Posted Yesterday

Role Overview

Cadence Design Systems is hiring a mid-level Mixed Signal Systems and Verification Engineer II. This is a full-time role in MOUNT-ROYAL (Montreal). posted yesterday. Full responsibilities, required qualifications, and the apply link are listed in the description below.

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Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This role is for an existing vacancy

Mixed‑Signal Systems and Verification Engineer II

At Cadence, we hire and develop leaders and innovators who want to make a meaningful impact on the future of technology. Our teams work on the world’s most advanced designs, enabling breakthroughs from high‑performance computing to artificial intelligence and machine learning.

The Mixed‑Signal Verification Team is seeking a Mixed‑Signal Systems and Verification Engineer II to contribute to the verification of complex digital and mixed‑signal designs. In this highly visible role, you will collaborate closely with analog, digital, and systems teams and play a critical role in delivering high‑quality silicon to market.

Cadence fosters a high‑performance culture that values creativity, innovation, and technical excellence. You will work alongside some of the brightest engineers in the industry while solving problems that matter.

Cadence has been recognized globally as a Great Place to Work and has been named one of the Fortune 100 Best Companies to Work For multiple times.

Responsibilities

Be part of a hands‑on development team that promotes engineering excellence, creativity, and innovation.
Develop accurate, simulation‑efficient analog and mixed‑signal behavioral models (RNM) in SystemVerilog.
Verify that behavioral models accurately represent analog schematics and design intent.
Integrate analog behavioral models with RTL environments.
Verify analog and mixed‑signal functionality against specifications using:
- SystemVerilog testbenches
- Test scenarios
- Assertions, including Analog Assertion‑Based Verification
Support verification of blocks such as filters, ADC/DAC, VCO, A/DPLL, SerDes, LNA, mixers, and related AMS IP.
Debug verification failures across analog, digital, and mixed‑signal domains.
Develop and maintain verification infrastructure including testbenches, environments, and scripts.
Document modeling assumptions, verification methodology, and results for formal design and verification reviews.
Collaborate cross‑functionally with design, systems, and IP teams to understand constraints and ensure verification coverage.

Required Qualifications

0–2+ years of experience working in digital, analog, or mixed‑signal design and verification environments.
Bachelor’s degree in Electrical Engineering or related field
(MSEE or PhD preferred).
Strong understanding of SystemVerilog and mixed‑signal verification concepts.
Experience or coursework in real‑number modeling (RNM) including:
- wreal
- UDN / UDT / UDR
- Verilog‑AMS
Basic understanding of analog and mixed‑signal blocks such as ADCs, DACs, PLLs, SerDes, RF or signal‑processing components.
Familiarity with Cadence Virtuoso Schematic Composer and ADE.
Strong written and verbal communication skills with the ability to work across teams.
Comfortable working in a fast‑paced, collaborative development environment.

Preferred Qualifications

Experience developing verification infrastructure (testbenches, environments, automation).
Experience scripting verification and design automation flows using Python or Perl.
Experience with low‑power architectures.
Exposure to SystemVerilog UVM methodologies.
Experience with FPGA prototyping.
Familiarity with industry standards such as PCIe, USB, DDR, or similar.
Knowledge of mixed‑signal Cadence tools and mixed‑signal verification methodologies.
Exposure to hardware acceleration platforms such as Palladium or Protium.
Experience with revision control systems (e.g., SOS, SVN).

Ingénieur(e) systèmes et vérification en signaux mixtes II

Chez Cadence, nous recrutons et développons des leaders et des innovateurs qui souhaitent avoir un impact significatif sur l’avenir de la technologie. Nos équipes travaillent sur les conceptions les plus avancées au monde, permettant des percées allant du calcul haute performance à l’intelligence artificielle et à l’apprentissage machine.

L’équipe de vérification en signaux mixtes recherche un(e) Ingénieur(e) systèmes et vérification en signaux mixtes II afin de contribuer à la vérification de circuits numériques et mixtes complexes. Dans ce rôle très critique, vous collaborerez étroitement avec les équipes analogiques, numériques et systèmes, et jouerez un rôle clé dans la mise sur le marché de circuits intégrés de haute qualité.

Cadence favorise une culture de haute performance qui valorise la créativité, l’innovation et l’excellence technique. Vous travaillerez aux côtés de certains des ingénieurs les plus talentueux de l’industrie tout en résolvant des problèmes qui comptent réellement.

Cadence est reconnue mondialement comme un excellent milieu de travail et a été nommée à plusieurs reprises parmi les 100 meilleures entreprises où travailler selon le classement Fortune.

Responsabilités

Faire partie d’une équipe de développement multidisciplinaire qui favorise l’excellence en ingénierie, la créativité et l’innovation.
Développer des modèles numériques de circuits analogiques et en signaux mixtes précis et efficaces en simulation (RNM) en SystemVerilog.
Vérifier que les modèles numériques représentent fidèlement les schémas analogiques et l’intention de conception.
Intégrer des modèles numériques analogiques dans des environnements RTL.
Vérifier les fonctionnalités analogiques et en signaux mixtes par rapport aux spécifications à l’aide de :
- Bancs de test SystemVerilog
- Scénarios de test
- Assertions, y compris la vérification basée sur des assertions analogiques
Soutenir la vérification de blocs tels que filtres, ADC/DAC, VCO, A/DPLL, SerDes, LNA, multiplexeurs, et autres IP AMS connexes.
Déboguer les problèmes de vérification dans les domaines analogique, numérique et mixte.
Développer et maintenir l’infrastructure de vérification, y compris les bancs de test, les environnements et les scripts.
Documenter les hypothèses de modélisation, la méthodologie de vérification et les résultats pour les revues formelles de conception et de vérification.
Collaborer de manière interfonctionnelle avec les équipes de conception, systèmes et IP afin de comprendre les contraintes et d’assurer une couverture de vérification adéquate.

Qualifications requises

0 à 2+ années d’expérience en conception et/ou vérification numérique, analogique ou en signaux mixtes.
Baccalauréat en génie électrique ou dans un domaine connexe
(Maîtrise ou doctorat en génie électrique préféré).
Solide compréhension de SystemVerilog et des concepts de vérification en signaux mixtes.
Expérience ou formation académique en modélisation à nombres réels (RNM), incluant :
- wreal
- UDN / UDT / UDR
- Verilog‑AMS
Compréhension de base des blocs analogiques et en signaux mixtes tels que ADC, DAC, PLL, SerDes, RF ou composants de traitement du signal.
Familiarité avec Cadence Virtuoso Schematic Composer et ADE.
Excellentes compétences en communication écrite et orale, avec la capacité de travailler en équipe.
À l’aise dans un environnement de développement collaboratif et dynamique.

Qualifications souhaitées

Expérience dans le développement d’infrastructures de vérification (bancs de test, environnements, automatisation).
Expérience en scripts pour les flux de vérification et d’automatisation de la conception (Python ou Perl).
Expérience avec des architectures électronique de basse consommation.
Connaissance des méthodologies UVM en SystemVerilog.
Expérience en prototypage FPGA.
Familiarité avec des normes industrielles telles que PCIe, USB, DDR ou équivalentes.
Connaissance des outils Cadence pour les signaux mixtes et des méthodologies de vérification associées.
Exposition à des plateformes d’accélération matérielle telles que Palladium ou Protium.
Expérience avec des systèmes de gestion de versions (p. ex. SOS, SVN, GIT).

The annual salary range is $ 73,500 .00 CAD to $136,500.00 CAD. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and holidays, leave of absence programs, Registered Retirement Savings Plan (RRSP), Tax Free Savings (TFSA) plan for post-tax investment savings, Employee Stock Purchase Plan, group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents. Cadence also offers employee and dependent Life insurance, and short-term and long-term disability. In addition, Cadence provides Global Travel Medical coverage, Business Travel Accident Insurance, and a funded Lifestyle Spending Account (LSA).

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Frequently Asked Questions

How do I apply for the Mixed Signal Systems and Verification Engineer II position at Cadence Design Systems?

Use the Apply button above to submit your application directly to Cadence Design Systems. Most applications take less than 5 minutes if your resume and contact details are ready, and you'll be routed to the employer's official application system to finish.

Where is the Mixed Signal Systems and Verification Engineer II position at Cadence Design Systems located?

This position is based in MOUNT-ROYAL (Montreal). Cadence Design Systems has not indicated remote or hybrid options for this role, so candidates should plan for on-site work.

What does a Mixed Signal Systems and Verification Engineer II at Cadence Design Systems earn?

Cadence Design Systems has not disclosed a salary range in this posting. Many employers share specifics later in the interview process; you can also ask during a recruiter screen if compensation transparency is important to you.

When was the Mixed Signal Systems and Verification Engineer II role at Cadence Design Systems posted?

This role was posted on July 21, 2026 (yesterday). It's still listed as actively hiring; we re-confirm openings against the source system multiple times per day and remove closed roles.