Staff Power Systems Safety Engineer

The Role

As the Staff Power Systems Safety Engineer, you are the ultimate technical authority on the electrical safety of Apollo’s power architecture.  Our flagship robot, Apollo, operates in highly dynamic environments, requiring high currents through a densely packaged, articulating chassis. We are scaling our engineering organization and looking for a hardware engineer to ensure that our power delivery networks are inherently, physically safe.

Key Responsibilities

Hardware Safety Architecture

• Safety Requirements Flow-Down: Translate top-level functional safety requirements into rigorous schematic-level constraints, safety-critical board-level layouts, and architectural definitions to guarantee deterministic hardware safety behavior.
• Architect Safety Functions: Formally design and own the hardware-enforced fail-safe safety pathways—such as Safe Torque Off (STO), Safe Brake Control (SBC), and Emergency Stop (E-stop) loops—ensuring strict compliance with Performance Levels (PLr per ISO 13849-1) and Safety Integrity Levels (SIL per IEC 61508/IEC 62061).
• Define the hardware/software boundary: design the physical signaling pathways and watchdogs that allow the high-current hardware to reliably inform the firmware of an impending fault, while ensuring the ultimate safety shutoff remains physically hardwired.

PCB & Interconnect Design Authority

• Enforce Design Rule Check (DRC) Standards: Establish electrical design standards for high-reliability packaging and assembly utilizing IPC-2221/IPC-2223 for trace routing/clearances and IPC-A-600/IPC-A-610 for board acceptability.
• PCB Stack-up & Thermal-Electrical Governance: Dictate PCB stack-ups, heavy-copper trace ampacity rules, and thermal-electrical limits for  power distribution boards,  motor drivers, and compute boards.
• Overcurrent Protection Coordination (IEC 60204-1): Architect multi-tiered fusing and protective strategies to guarantee complete fault coordination, ensuring protection elements predictably interrupt fault paths before conductor insulation, wire harnesses, or PCB laminate layers reach degradation or glass transition thresholds.

Risk Analysis, Root Cause, & Auditing

• Safety Gatekeeper: Serve as the absolute sign-off authority on all engineering change releases and tape-outs affecting system power or functional safety, preserving final veto power over any assembly violating critical safety margins.
• Rigorous Safety Analytics: Author and manage specialized compliance safety documentation, directly executing and owning hardware-focused Design Failure Mode and Effects Analyses (DFMEAs), Hazard Analysis and Risk Assessments (HARA), and Fault Tree Analyses (FTAs).
• Worst-Case Circuit Analysis (WCCA): Utilize SPICE-based simulation tools to mathematically prove design performance margins across manufacturing component tolerances, extreme operating temperatures, and structural lifetime aging metrics.
• Root Cause Forensics: Direct engineering investigations and teardowns for power delivery anomalies, mechanical stress limits, thermal events, or localized component degradations discovered during Hardware-in-the-Loop (HIL) qualification, laboratory evaluation, or active fleet deployments.

Third-Party Certification & External Lab Management

• Certification Strategy: Own the end-to-end hardware compliance roadmap, determining exactly which external lab tests are required for global market access (e.g., UL, CE, CSA).
• NRTL Liaison: Act as the primary technical authority and negotiator with Nationally Recognized Testing Laboratories (NRTLs) like UL, TUV, or Intertek. Defend Apollo’s electrical safety architecture and negotiate the interpretation of novel or vague standards (like UL 3300) applied to humanoid platforms.
• Test Readiness & Fixturing: Oversee the design of specialized breakout boards, dummy loads, and fault-injection fixtures required by external labs to safely test catastrophic failures (e.g., inducing a dead short or thermal runaway) without destroying the entire robot.
• On-Site Execution & Triage: Lead the engineering response during formal lab testing. When a component fails a destructive test on-site, act rapidly to diagnose the physical failure, propose a hardware mitigation, and negotiate a path forward with the lab inspector to maintain certification timelines.

Job Requirements

• Education: BS, MS, or PhD in Electrical Engineering, Power Electronics, or a related discipline.
• Experience: 8+ years of hardware design engineering, with a minimum of 2 years as a lead architect or staff-level engineer designing high-current power distribution, EV powertrains, or high-reliability industrial power systems.
• Certification Experience: Proven track record of directly managing third-party testing and successfully securing hardware certifications (UL, CE, TUV) for complex electromechanical systems.
• Domain Expertise:
• Mastery of PCB design best practices and standards, such as IPC.
• Extensive experience designing fail-safe analog circuits, redundant safety architectures, and hardware-based interlocks.
• Standards Knowledge: Strong practical understanding of hardware safety standards (ISO 13849-1, IEC 61508, IEC 60204-1, UL 3300, IEC 62368) and how to translate them into schematic-level requirements and lab test plans.
• Lab Skills: Highly proficient with high-power test equipment (programmable electronic loads, thermal imaging, high-current power supplies) and designing automated test fixtures for fault injection.
• Soft Skills: Exceptional ability to distill complex risk mathematics into actionable design constraints. You must be able to hold your ground in design reviews, negotiate with external compliance inspectors, and drive alignment across Mechanical and Firmware engineering teams.

PHYSICAL REQUIREMENTS

• Prolonged periods of sitting at a desk and working on a computer 
• Must be able to lift 15 pounds at times
• Vision to read printed materials and a computer screen
• Hearing and speech to communicate