Staff Engineer, Digital ASIC Design

Company Description

At Butterfly Network, we’re leading a digital revolution in medical imaging, transforming an industry that has long relied on bulky, analog systems. With our proprietary Ultrasound-on-Chip™ technology, we’re democratizing healthcare by shifting ultrasound from the expensive, stationary systems of the past to the connected, mobile, and software-enabled platforms of today.  In 2018, we launched the world’s first handheld, whole-body ultrasound, Butterfly iQ – followed by iQ+ in 2020 and iQ3 in 2024, each more powerful than the last.

Our innovation doesn’t stop at hardware. Butterfly combines our advanced device with intelligent software, AI, services, and education to drive adoption of affordable, accessible imaging. Our technology is proving to help clinicians, clinics, and hospitals enhance care, cut costs, and expand imaging access. We’ve been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions, Fast Company’s World Changing Ideas, among other awards.

We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together!

Job Description

The role of the Principal Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.

As part of our team, your core responsibilities will be: 

• Develop low-power RTL for large SoCs in an advanced node.
• Implement and optimize signal processing algorithms in RTL.
• Integrate multiple embedded processor cores into a large design.
• Develop efficient high bandwidth on chip data paths.
• Other Technology, Architecture, & Productivity duties as assigned

Qualifications

Baseline skills/experiences/attributes:

• BS/MS/PhD in EE/CE (or equivalent practical silicon design experience).
• 8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle.
• Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support.
• Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
• Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations.
• Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs.
• Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb).
• Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking.
• Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes.
• Strong cross-functional communication to close hardware–firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders.

Ideally, you also have these skills/experiences/attributes (but it’s ok if you don’t!):

• Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline.
• Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines and image-quality KPIs.
• Advanced-node experience (28nm or smaller), including timing sensitivity and third-party IP integration.
• (Optional, only if this matches the role) Experience integrating programmable compute subsystems (MPU/accelerator), including control interfaces and memory/bandwidth tradeoffs.

Values

Innova